1. Field of the Invention
The present invention relates to an apparatus and method for time alignment of an Envelope Tracking (ET) Radio Frequency (RF) Power Amplifier (PA). More particularly, the present invention relates to an apparatus and method for a time alignment operation used by a ET RF PA that amplifies RF signals.
2. Description of the Related Art
In recent years, the use of mobile communications using wireless communication networks has become widespread, thus, increasing a demand for faster, higher bandwidth, and more efficient wireless communication networks. The wireless communication networks communicate using RF signals propagated in the wireless communication networks that may be divided into communication cells. The communication cells, providing wireless communication to mobile devices located in respective coverage areas of the communication cells, may include Base Stations (BSs) that include RF transmitters and Digital Signal Processing (DSP) units. The RF transmitters include power amplifiers in order to amplify the RF signals propagated in the communication cells in order to perform wireless communication between the BSs and the mobile devices located in the respective coverage areas. The DSP units provide processing of the RF signals that are to be transmitted by the RF transmitters according to algorithms of the DSP units.
Time Alignment (TA) algorithms which are suitable for the ET RF PA, are DSP algorithms that can be implemented via software so as to run or be executed on specialized processors such as a DSP-Central Processing Unit (CPU). Alternatively, the TA algorithms may be implemented via hardware so as to run or be executed on purpose-built hardware processors such as field-programmable gate arrays (FPGAs). Furthermore, the TA algorithms may be implemented via a combination of software and hardware. TA algorithms present considerable challenges towards achieving a cost-effective DSP implementation. The TA algorithms are based on cross-correlation/cross-covariance techniques, and thus, the TA algorithms present a high computational complexity require large amounts of silicon resources of FPGAs or large amounts of computation time of the DSP-CPU.
The TA algorithms are computed in order to perform the TA operation, and a critical parameter of the TA algorithms is a time resolution of the TA computation. The time resolution of the TA computation may be of an order or magnitude that is 20 times a sampling rate of the system. In order to achieve optimal ET performance in the ET-PA, a time mismatch sensitivity should be in a range of 200 picoseconds to 400 picoseconds. However, such a range for the time mismatch sensitivity requires a high time resolution. Furthermore, the high time resolution for the TA computation uses a cross-correlation function performed with high accuracy in order to determine an accurate peak location. Because the computational accuracy is proportional to a signal length captured by the DSP system, wherein the signal length is N samples long, the TA computation will involve the processing of large data arrays stored in memory.
The processing of the large data arrays resulting from the high time resolution makes the implementation of the TA algorithm impractical. Accordingly, many implementations of the TA algorithms rely upon incremental adjustments that use multiple measurements of the RF signal in conjunction with an iterative process. Beside the iterative process, other implementation of the TA algorithm may use an off-line technique, wherein the estimation is performed during a calibration step occurring before real time operations using the cross-correlation function. However, in the off-line technique, consideration is not given to temperature variations during the real time operation. In addition, if any variant from the off-line technique is suitable for on-line operation, it requires processing the cross-correlation estimation two times, which substantially increases computation time.
In order to satisfy the growing demand for wireless communications and wireless services, highly linear multi-carrier RF and/or microwave transmitters having high power efficiency and increasingly sophisticated circuit topologies are being developed. These topologies combine an efficient distortion compensation technique, such as Digital Pre-Distortion (DPD), with high efficiency power amplification techniques, such as Envelope Elimination and Restoration (EER), Envelope Tracking (ET), Doherty power amplification, switching mode families, or other similar amplification techniques, and the TA algorithms play important role in all of the above noted distortion compensation techniques and the power amplification techniques.
FIG. 1 is a block diagram of high efficiency signal amplification according to the related art.
Referring to FIG. 1, the illustrated process of high-efficiency signal amplification may be suitable for EER and ET amplifier systems. The ET amplifier system 101 uses an envelope path 102, which includes a DC power supply 103 capable of delivering modulation power throughout the bias of a conventional Class AB Power Amplifier (PA). During the amplification process, a complex signal is sent through a forward path 104, while a corresponding envelope waveform is simultaneously sent through the envelope path 102 to drive the PA bias. A feedback path 105 is used to monitor the PA performance and to capture a batch of data output from the PA in order to perform DPD modeling and TA.
As shown in FIG. 1, the ET amplifier system also includes a DSP environment containing a DSP-Central Processing Unit (DSP-CPU) 106 to process both the DPD modeling and TA estimation, a DPD processor 107 for nonlinear distortion cancellation, and four TA units for time mismatch cancellation. The four TA blocks include an envelope fractional delay 108, a forward coarse delay 109, a feedback fractional delay 110, and a reference coarse delay 111. In addition, the ET amplifier includes a digital envelope detector 112 cascaded with an envelope modulator in the envelope path, an up-converter 113 followed by a RF-PA 114 in the forward path, and a down converter 115 in the feedback path. A signal processing block 116, which is disposed at the input of the ET amplifier system 101 so as to be before the DPD block 107 performs filtering, interpolation and Crest Factor Reduction functions.
The PA using ET performs with better power efficiency than PAs of the related art and/or PAs using other related art power amplification techniques. However, an Adjacent Channel Leakage Ratio (ACLR) at the output of the PA using ET is highly sensitive to a delay mismatch between the envelope path and the forward path to the PA. To mitigate a time mismatch resulting from the delay mismatch, the ET system may use a delay control for the envelope and forward paths. It should be noted that the time mismatch between a reference signal and a feedback signal does not have a direct impact on ET performance. However, the time mismatch between the reference signal and the feedback signal does have an effect on the DPD modeling for the DPD model located in the DPD block of the PA using ET. A time mismatch included in the modeling process affects the characteristic of the distortion generated by the DPD model which is used to cancel distortion from the PA nonlinearity.
The computation time of the TA algorithm is a critical parameter for an on-line technique for computing the TA algorithm. Accordingly, a program speed for a program running the algorithm depends on how the digital hardware, such as the DSP processor, processes the data. A typical DSP processor includes a high-speed on-chip memory to allow for quick access to stored data, such as the data arrays for signal processing. However, when the data arrays to be used by the TA algorithm are too large for the on-chip memory, the data arrays need to be constantly moved from being stored in the on-chip memory to being stored in an off-chip external memory. The data arrays used for a highly accurate cross-correlation method having a large number of samples may be too large to store on the on-chip memory, and thus may be subject to being constantly moved from the on-chip memory to the off-chip memory during a DSP operation. As a result, a program flow is slowed such that the computation time is increased. The slow program flow and increased computation time has a direct impact on the ET performance when parameter adaptation of the TA algorithm or data array is performed.
Accordingly, there is a need for an apparatus and method for implementing an algorithm that employs a low number of samples in the TA computation in order to allow use of a high-speed on-chip memory, wherein the small size of data does not produce a performance penalty producing poor results for the TA computation. In addition, it is desirable to have an algorithm that could efficiently extract data objects, representative of the time mismatch information, from large data structures stored in the external memory. It is also desirable to have an algorithm that quickly responds to temperature or other physical variations.